Through a press release on their website, the PCI Express Special Interest Group (PCI-SIG) has announced that it has finalized its PCI Express 2.0 specifications. The specifications initially entered the release candidate stage a little over three months ago.

The new PCI Express 2.0 Bus Specification doubles the interconnect bit rate from 2.5 GT/s to 5 GT/s. The PCI-SIG describes this as “by far the most important feature of the PCI Express 2.0 specifications.” Doubling the interconnect bit rate increases the aggregate bandwidth of a single PCI Express x16 slot to 16 GB/s. PCI Express 2.0 is also backwards compatible with older versions of the standard, meaning that consumers will still be able to use their older hardware in slots based on the revised standard.  

In addition to the bandwidth increase, the new specifications have a number of other improvements. Dynamic link speed management has been added allowing software to control the speed at which Express 2.0 links are operating. Under the new specification, software is also notified of changes in link speed and width. The Express 2.0 interface also implements a new feature that gives software optional controls to manage packet routing on the interconnect. The power limit can now also be redefined in order “to accommodate devices that consume higher power.”

The new interface will prove to be particularly useful for video cards whose performance is limited as a result of lower I/O throughput. Manufacturers will be able to use the faster channels for shared memory graphics which uses system memory to boost performance.